1. Field of the Invention
The invention relates to semiconductor integrated circuits and, more particularly, to internal test circuitry of a semiconductor integrated circuit.
2. Background of the Invention
Semiconductor integrated circuits are typically tested in response to an applied input test signal. The semiconductor integrated circuits respond to the input test signal by providing a test output signal which is monitored to determine if the part has been manufactured correctly. With an increase in storage capacity and memory circuit functions, the testing of a semiconductor integrated circuit consumes more time and requires more testing hardware.
In FIG. 1, a memory component tester 5 of the related art is shown which has four test stations 7-10. Each test station 7-10 is used to test circuit functions of an individual semiconductor integrated circuit or, during testing known as, a device under test (DUT). Therefore when testing, say, four integrated circuits 12-15, as shown in FIG. 1, four test stations 7-10 are needed. Typically, each test station 7-10 has a number of pins 20 corresponding to the number of I/O (input/output) pins 25 on the DUT for coupling the test station to the DUT during testing. The DUT responds to applied test signals originating in the memory component tester 5 and generates test output signals in response to the applied test signals. The test stations monitor the test output signals to determine if a DUT has been manufactured correctly.
The ability to test in parallel is limited by the number of Pin Electronic Channels with comparator capability a memory component tester may have. How those limited resources are utilized by the product tested on test equipment is directly related to designing a test mode which makes best use of each Pin Electronics Channel. The present Micron Test Mode tri-states each unique I/O pin individually upon failure. This prevents the tying of multiple I/O pins together for greater parallel testing because a failing pin in a high impedance state is driven by a passing pin to a passing voltage level. The driving pin (Passing) would mask the tri-stated (failing) pin which would cause the failure to go undetected, and the failed part would be binned with those which passed testing.
In order to reduce the total manufacture time and decrease manufacturing costs there is a need to develop a faster testing method requiring less test equipment.
The invention is a semiconductor integrated circuit, method and test system for compressing test stimuli to one test output signal during a test mode. The test output signal is driven from one input/output node of the semiconductor integrated circuit to a test station through a load board interface of the invention. Buffer circuitry on the semiconductor integrated circuit drive a high impedance to the input/output nodes of the integrated circuit during the test mode. The load board interface allows a single test station to receive test output signals from a plurality of semiconductor integrated circuits of the invention during the test mode, thereby allowing one test station to simultaneously test a plurality of circuits.